DTA

Digital Theses Archive

 

Tesi etd-09082019-124151

Type of thesis
Dottorato
Author
PAGANI, MARCO
URN
etd-09082019-124151
Title
Enabling predictable hardware acceleration in heterogeneous SoC-FPGA computing platforms
Scientific disciplinary sector
ING-INF/05
Course
INGEGNERIA - Ph.D. Programme in Emerging Digital Technologies (EDT)
Committee
Membro Prof. BUTTAZZO, GIORGIO CARLO
Membro Prof. HENKEL, JöRG
Presidente Prof. NIAR, SMAIL
Membro Prof. LIPARI, GIUSEPPE
Membro Prof. ABENI, LUCA
Membro Dott.ssa CUCU-GROSJEAN, LILIANA
Membro Prof. BARUAH, SANJOY
Membro Prof.ssa PALUMBO, FRANCESCA
Keywords
  • Dynamic partial reconfiguration
  • Hardware acceleration
  • Heterogeneous platforms
  • Real-time systems
  • SoC-FPGA
Exam session start date
;
Availability
parziale
Abstract
Modern computing platforms for embedded systems are evolving towards heterogeneous architectures comprising different types of processing elements and accelerators. Such an evolution is driven by the steady increasing computational demand required by modern cyber-physical systems. These systems need to acquire large amounts of data from multiple sensors and process them for performing the required control and monitoring tasks. These requirements translate into the need to execute complex computing workloads such as machine learning, encryption, and advanced signal processing algorithms, within the timing constraints imposed by the physical world. Heterogeneous systems can meet this computational demand with a high level of energy efficiency by distributing the computational workload among the different processing elements.<br><br>This thesis contributes to the development of system support for real-time systems on heterogeneous platforms by presenting novel methodologies and techniques for enabling predictable hardware acceleration on SoC-FPGA platforms. The first part of this thesis presents a framework designed for supporting the development of real-time applications on SoC-FPGAs, leveraging hardware acceleration and logic resource &#34;virtualization&#34; through dynamic partial reconfiguration. The proposed framework is based on a device model that matches the capabilities of modern SoC-FPGA devices, and it is centered around a custom scheduling infrastructure designed to guarantee bounded response times. This characteristic is crucial for making dynamic hardware acceleration viable for safety-critical applications. The second part of this thesis presents a full implementation of the proposed framework on Linux. Such implementation allows developing predictable applications leveraging the large number of software systems available on GNU/Linux while relying on dynamic FPGA-based hardware acceleration for performing heavy computations. Finally, the last part of this thesis introduces a reservation mechanism for the AMBA AXI bus aimed at improving the predictability of hardware accelerators by regulating BUS contention through a bandwidth reservation mechanism.
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