DTA

Digital Theses Archive

 

Tesi etd-09212017-100658

Thesis type
Dottorato
Author
ROSSI, ENRICO
URN
etd-09212017-100658
Title
Towards the heterogeneous, real-time reconfigurable embedded system
Scientific disciplinary sector
ING-INF/01
Corso di studi
INGEGNERIA - Ph.D. Programme in Emerging Digital Technologies (EDT)
Commissione
relatore Prof. BUTTAZZO, GIORGIO CARLO
Membro Prof. ARSLAN, TUGHRUL
Presidente DI NATALE, MARCO
Membro Prof. DRAGONI, ALDO FRANCO
Parole chiave
  • FPGA
  • FPGA reconfiguration preemption
  • Partial Reconfiguration
  • real-time guarantees
  • real-time reconfiguration
Data inizio appello
;
Disponibilità
completa
Riassunto analitico
To improve the computing performance in real-time applications, modern embedded<br>platforms comprise hardware accelerators that speed up the tasks’ most computeintensive<br>parts. A recent trend in the design of real-time embedded systems is to<br>integrate field-programmable gate arrays (FPGA) that are reconfigured with different<br>accelerators at runtime, to cope with dynamic workloads that are subject to timing<br>constraints, like in signal processing or computer vision applications.<br>One of the major limitations when dealing with partial FPGA reconfiguration in realtime<br>systems is that the reconfiguration port can only perform one reconfiguration at a<br>time: if a high-priority task issues a reconfiguration request while the reconfiguration<br>port is already occupied by a lower-priority task, the high-priority task has to wait until<br>the current reconfiguration is completed (a phenomenon known as priority inversion),<br>unless the current reconfiguration is aborted (introducing unbounded delays in lowpriority<br>tasks, a phenomenon known as starvation).<br>Moreover, hardware accelerators reconfigured at runtime inside the FPGA usually<br>require minimum interaction with the software side and perform massive computations<br>on data which have to be read from the main memory or written to it. Therefore, In<br>case of high-throughput hardware accelerators may happen that the communication<br>medium shared between main memory and hardware and software sides is not able to<br>accept more requests jeopardizing the functioning of the whole system. Furthermore,<br>as the software can not control each bus transaction of an hardware accelerator, mis-designed accelerators could perform illegal memory accesses corrupting the main<br>memory.<br>This thesis shows how priority inversion and starvation can be solved by making<br>the reconfiguration process preemptive, i.e., allowing it to be interrupted at any time<br>and resumed at a later time without restarting it from scratch. Such a feature is crucial<br>for the design of runtime reconfigurable real-time systems, but not yet available in<br>today’s platforms. Furthermore, the trade-off of achieving a guaranteed bound on<br>the reconfiguration delay for low-priority tasks and the maximum delay induced for<br>high-priority tasks when preempting an ongoing reconfiguration has been identified<br>and analyzed.<br>Besides, this work addresses the problems of memory protection and bus predictability<br>by showing a solution to prevent hardware accelerators from choking the<br>communication bus or performing illegal memory accesses, making the communication<br>more predictable and allowing for more precise analysis. A custom memory protection<br>and budgeting unit (MPBU) has been developed for this purpose.<br>Experimental evaluation on the Xilinx Zynq-7000 platform have been realized for<br>preemptive reconfiguration and MPBU. Results show that the proposed implementation<br>of preemptive reconfiguration introduces a low runtime overhead, thus effectively<br>solving priority inversion and starvation. Moreover, experimental results show that<br>memory corruption and bus chocking problems can be avoided and the communication<br>over a shared bus can be made more predictable allowing to have less stringent timing<br>constraints in the analysis.
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