Tesi etd-09252024-123051
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Tipo di tesi
Dottorato
Autore
STEVANATO, ANDREA
URN
etd-09252024-123051
Titolo
Enhancing Predictability in Mixed-Criticality Cyber-Physical Systems: Addressing Memory Contention and Communication Challenges
Settore scientifico disciplinare
ING-INF/05
Corso di studi
Istituto di Tecnologie della Comunicazione, dell'Informazione e della Percezione - PHD IN EMERGING DIGITAL TECHNOLOGIES
Relatori
relatore BUTTAZZO, GIORGIO CARLO
tutor Prof. BIONDI, ALESSANDRO
tutor Prof. BIONDI, ALESSANDRO
Parole chiave
- real-time systems
- timing predictability
Data inizio appello
10/06/2025;
Disponibilità
parziale
Riassunto analitico
The integration of mixed-criticality applications within Cyber-Physical Systems (CPS) is increasingly challenging due to the different levels of safety and security requirements, resource contention, and real-time constraints imposed by automotive and industrial systems. This thesis investigates key challenges in virtualization, memory contention, and GPU real-time scheduling proposing novel solutions that enhance both communication efficiency and timing predictability in CPS.
A first contributing is the development of a virtualized communication architecture for the Data Distribution Service (DDS) middleware, which is widely used for interconnecting distributed software components. Leveraging hypervisor technology, the proposed architecture allows optimized inter-domain DDS-based communication within the same hardware platform. We demonstrate the feasibility of this approach by implementing it on the Xen hypervisor and Linux operating system, where a systematic analysis of various architectural configurations and an in-depth performance evaluation demonstrate significant improvements in inter-domain communication.
The second key contribution is FrATM2, a framework developed to address the unpredictability caused by memory contention in Commercial Off-The-Shelf (COTS) multi-core systems. Memory interference, particularly at the Memory Controller (MC) level, can drastically affect the worst-case response times of real-time applications. FrATM2 automatically generates and executes micro-benchmarks applications to profile the MC's behavior under a wide range of contention scenarios, allowing the learning of accurate timing models. These models provide critical insights for bounding memory-related interference and improving real-time analysis in multi-core CPS.
Finally, the thesis introduces a GPU-accelerated framework for Deep Neural Network (DNN) inference on GPU-based embedded platform. Traditional GPU inference frameworks prioritize throughput over timing guarantees, which can compromise the predictability of time-sensitive tasks. To overcome this, the framework combines a design-time optimization of DNN workloads with an ad-hoc real-time scheduler to ensure the deterministic scheduling of GPU acceleration requests. The proposed framework significantly enhances the timing predictability for real-time applications requiring concurrent DNNs executions.
Through comprehensive experimental evaluations on industry-standard hardware, this thesis provides a robust foundation for improving the predictability and safety of mixed-criticality CPS systems.
A first contributing is the development of a virtualized communication architecture for the Data Distribution Service (DDS) middleware, which is widely used for interconnecting distributed software components. Leveraging hypervisor technology, the proposed architecture allows optimized inter-domain DDS-based communication within the same hardware platform. We demonstrate the feasibility of this approach by implementing it on the Xen hypervisor and Linux operating system, where a systematic analysis of various architectural configurations and an in-depth performance evaluation demonstrate significant improvements in inter-domain communication.
The second key contribution is FrATM2, a framework developed to address the unpredictability caused by memory contention in Commercial Off-The-Shelf (COTS) multi-core systems. Memory interference, particularly at the Memory Controller (MC) level, can drastically affect the worst-case response times of real-time applications. FrATM2 automatically generates and executes micro-benchmarks applications to profile the MC's behavior under a wide range of contention scenarios, allowing the learning of accurate timing models. These models provide critical insights for bounding memory-related interference and improving real-time analysis in multi-core CPS.
Finally, the thesis introduces a GPU-accelerated framework for Deep Neural Network (DNN) inference on GPU-based embedded platform. Traditional GPU inference frameworks prioritize throughput over timing guarantees, which can compromise the predictability of time-sensitive tasks. To overcome this, the framework combines a design-time optimization of DNN workloads with an ad-hoc real-time scheduler to ensure the deterministic scheduling of GPU acceleration requests. The proposed framework significantly enhances the timing predictability for real-time applications requiring concurrent DNNs executions.
Through comprehensive experimental evaluations on industry-standard hardware, this thesis provides a robust foundation for improving the predictability and safety of mixed-criticality CPS systems.
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