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Tesi etd-11142022-164748

Tipo di tesi
Corso Ordinario Secondo Livello
Autore
ORIGLIA, MARCO
URN
etd-11142022-164748
Titolo
FPGA design of a multidimensional reconciliation encoder for a continuous variable quantum key distribution system
Struttura
Cl. Sc. Sperimentali - Ingegneria
Corso di studi
INGEGNERIA - INGEGNERIA
Commissione
relatore Prof. BUTTAZZO, GIORGIO CARLO
Tutor Prof. FORESTIERI, ENRICO
Relatore Prof. SECONDINI, MARCO
Presidente Prof. AVIZZANO, CARLO ALBERTO
Membro Dott. LEONARDIS, DANIELE
Membro Prof. CIPRIANI, CHRISTIAN
Membro Prof. DI PASQUALE, FABRIZIO CESARE FILIPPO
Membro Prof.ssa MENCIASSI, ARIANNA
Membro Prof. MICERA, SILVESTRO
Membro Prof. VITIELLO, NICOLA
Membro Prof. ABENI, LUCA
Membro Prof. BIONDI, ALESSANDRO
Membro Prof. CUCINOTTA, TOMMASO
Membro Dott.ssa COLLA, VALENTINA
Parole chiave
  • FPGA
  • QKD
  • LDPC
  • Information Theory
  • Information Reconciliation
  • error correction
  • Chisel-HDL
  • Scala
Data inizio appello
14/12/2022;
Disponibilità
parziale
Riassunto analitico
In the future, quantum computing will allow computational heavy tasks to be solved in very short times. Since current cryptographic schemes are computationally secure, meaning that breaking them is unfeasible with the current technology, they may become insecure in the wake of quantum computing. This concern has pushed researchers and industries to search for an unconditionally secure cryptographic scheme. A promising solution comes again from quantum physics, that enables physically (thus unconditionally) secure symmetric key distribution schemes. The task of sharing a symmetric key in a secure way exploiting quantum physics is called Quantum Key Distribution (QKD).

Such a task includes two post-processing phases: information reconciliation to correct possible key errors, and privacy amplification, to reduce the leaked information during the preceding phases. The purpose of multidimensional reconciliation is to recover a randomly generated bit stream from correlated Gaussian data exchanged in a quantum channel. The bit stream can then be used as the input of the privacy amplification sub-task.

It is important to process keys as fast as possible to increase the key generation rate, as a greater key rate implies greater security. Key post processing may be accelerated with FPGAs. My work is about an FPGA design of the encoder-side processing for information reconciliation. Processing is aimed at a continuous variable QKD system and enables multidimensional reconciliation. The design employs Chisel HDL, a set of Scala libraries, to describe hardware, then simulate and test its behaviour
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