Tesi etd-12132022-142207
Link copiato negli appunti
Tipo di tesi
Dottorato
Autore
BORROMEO, JUSTINE CRIS
URN
etd-12132022-142207
Titolo
Programmable Hardware Acceleration in 2D and 3D 5G Networks
Settore scientifico disciplinare
ING-INF/03
Corso di studi
Istituto di Tecnologie della Comunicazione, dell'Informazione e della Percezione - PHD IN EMERGING DIGITAL TECHNOLOGIES
Commissione
relatore VALCARENGHI, LUCA
Presidente Dott.ssa CRESPO, MARIA LIZ
Membro Dott. BASSOLI, RICCARDO
Presidente Dott.ssa CRESPO, MARIA LIZ
Membro Dott. BASSOLI, RICCARDO
Parole chiave
- 5G Network
- Field Programmable Gate Array
- hardware acceleration
- Three-dimensional Network
- Two-dimensional Network
- Unmanned Aerial Vehicle
Data inizio appello
28/04/2023;
Disponibilità
completa
Riassunto analitico
The evolution of the 5G communication network aims to support services based on three major used case scenarios namely (i) enhanced mobile broadband (eMBB), (ii) massive machine-type communications (mMTC), and (iii) ultra-reliable low-latency communications (URLLS). Through a 3D network, it also plans to provide internet connectivity to areas not covered by 5G terrestrial stations specifically in unserved/underserved zones, disaster-hit regions, and hotspot areas.
One of the main technological advancements that are implemented in 5G networks is the use of Network Function Virtualization (NFV) and Software Defined Networking (SDN) with the aim to provide fast and cost-effective network deployment, upgrade, and scaling of 5G functions. However, running computationally expensive functions in a virtualized environment or in Commercial-of-the-shelf (COTS) hardware like CPU may require additional CPU cycles, resulting in a longer processing time. This thesis aims to address this issue by implementing a programmable hardware accelerator in the edge data center of 2D and 3D 5G networks. Field Programmable Gate Arrays (FPGA) and Graphics Processing Units (GPU) are exploited as hardware accelerators in the 5G Radio Access Network (RAN) and Core Network to improve processing time and energy consumption.
Results showed that exploiting hardware acceleration to perform 5G functions that require high computational power helps to improve the processing time and energy consumption of 3D and 3D networks. The hardware acceleration is performed on the Lower Physical Layer of the RAN in an FPGA-based SmartNIC using Open Computing Language (OpenCL) framework, and on the application layer implementing physical distancing application in an NVIDIA Tesla T4 GPU.
One of the main technological advancements that are implemented in 5G networks is the use of Network Function Virtualization (NFV) and Software Defined Networking (SDN) with the aim to provide fast and cost-effective network deployment, upgrade, and scaling of 5G functions. However, running computationally expensive functions in a virtualized environment or in Commercial-of-the-shelf (COTS) hardware like CPU may require additional CPU cycles, resulting in a longer processing time. This thesis aims to address this issue by implementing a programmable hardware accelerator in the edge data center of 2D and 3D 5G networks. Field Programmable Gate Arrays (FPGA) and Graphics Processing Units (GPU) are exploited as hardware accelerators in the 5G Radio Access Network (RAN) and Core Network to improve processing time and energy consumption.
Results showed that exploiting hardware acceleration to perform 5G functions that require high computational power helps to improve the processing time and energy consumption of 3D and 3D networks. The hardware acceleration is performed on the Lower Physical Layer of the RAN in an FPGA-based SmartNIC using Open Computing Language (OpenCL) framework, and on the application layer implementing physical distancing application in an NVIDIA Tesla T4 GPU.
File
| Nome file | Dimensione |
|---|---|
| PhD_Diss...romeo.pdf | 15.06 Mb |
Contatta l'autore |
|